The present invention relates to a method of manufacturing a semiconductor device, more particular, to a method of manufacturing a semiconductor device related to alignment of a wiring pattern or the like and a hole pattern.
When the minimum size of an LSI pattern becomes close to a resolution limit in optical lithography, the fidelity of a resist pattern to a mask pattern is degraded, or line width of the resist size becomes abnormal. That is, a so-called optical proximity effect (OPE) becomes conspicuous.
FIGS. 1A and 1B show this optical proximity effect, in which FIG. 1A shows the design (design patterns) of a wiring pattern and a hole pattern (via hole or contact hole) and FIG. 1B shows a pattern on a wafer exposed by using a mask formed on the basis of the design in FIG. 1A.
A wiring pattern 11 has a straight portion and a bent portion, and a hole pattern 12 is generally arranged at the bent portion of the wiring pattern 11. The wiring pattern 11 and the hole pattern 12 are formed on different layers, respectively. A mask is formed according to the wiring pattern 11, and exposure is performed by using this mask to form a wiring pattern 13, as shown in FIG. 1B. Similarly, a mask pattern is formed according to the hole pattern 12, and exposure is performed by using this mask to form a hole pattern 14 on the wafer, as shown in FIG. 1B.
When the wiring pattern and the hole pattern have pattern sizes, which are close to the resolution limit in optical lithography, the optical proximity effect becomes conspicuous, and as shown in FIG. 1B, the corner of the bent portion of the wiring pattern 13 on the wafer has a conspicuous round shape. For this reason, the wiring pattern 13 is transferred to a position offset from an ideal wiring pattern 13a obtained in a state being free from the optical proximity effect. The hole pattern 14 also becomes round at a rectangular corner to obtain a circular pattern. As a result, the wiring pattern 13 is offset from the hole pattern 14 to cause the characteristics, reliability, and the like to be considerably degraded.
FIGS. 2A and 2B show optical proximity correction (OPC) which is developed as a means for solving the above problem. This optical proximity correction is performed to automatically add a fine pattern (serif pattern) which cannot be resolved to a mask. FIG. 2A show the design of a wiring pattern and a hole pattern (a via hole or a contact hole) and FIG. 2B shows a pattern on a wafer exposed by using a mask formed on the basis of the design in FIG. 2A.
According to the method using this optical proximity correction, a serif pattern 15 is formed in correspondence with the bent portion of the wiring pattern 11 such that a pattern desired by a designer is obtained as a pattern formed on a wafer, as shown in FIG. 2A. When the serif pattern 15 is formed as described above, as shown in FIG. 2B, the wiring pattern 13 transferred onto the wafer can be made close to the ideal wiring pattern 13a. As a result, the relative offset between the wiring pattern 13 and the hole pattern 14 can be corrected.
However, by adding the serif pattern 15, the mask data of the wiring pattern 11 considerably increases in comparison with a pattern 11a, which has no serif pattern 15. In addition, a pattern having a size smaller than a general pattern size must be formed on the mask.
As described above, when the wiring pattern or the hole pattern has a pattern size being close to a resolution limit in optical lithography, an optical proximity effect becomes conspicuous. For this reason, the corner of the bent portion of the wiring pattern transferred onto the wafer becomes conspicuously round, and the wiring pattern and the hole pattern are offset from each other, thereby causing the characteristics, reliability, and the like to be considerably degraded. Although a method of forming a serif pattern to solve this problem is also proposed, an amount of mask data becomes great, and a mask forming must receive a lot of load.